1. Technical Field
This disclosure generally relates to computer hardware testing and development, and more specifically relates to a system and method for stress testing a processor memory with a link stack using link stack test segments with non-naturally aligned data boundaries.
2. Background Art
Processor testing tools attempt to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be able to stress various timing scenarios and operations on the processor, including the coherency of cache memory. Coherency in the cache memory involves insuring that changes to data in the cache are accurately reflected to main memory to keep the data consistent. Building test cases to thoroughly test a processor can be extremely costly in time and resources, thus building efficient test cases that can reuse test code is an important goal of processor testing.
Many processors have a link stack that stores return addresses when executing a branch in the code. A link register is typically used to access the last entry into the link stack. The processor may make predictions of software execution based on the content of the link stack to speed execution. Also, there are often limits to the depth of the link stack. Accommodations in the test software must be made to deal with errors that may be generated when the link stack depth is exceeded. It is very difficult to generate test cases for memory that can also test the different scenarios of the link stack depth. Prior art test case generation was extremely labor intensive to develop stress tests for memory with different link stack depth scenarios.